The ever-increasing use of mobile communications is driving improvements in radio frequency (RF) communications. In particular, this expanding market is demanding lower power consumption and increased performance.
One possible solution that has found many applications is bipolar complementary metal-oxide semiconductor (BiCMOS) technology. In standard bipolar complementary metal-oxide-semiconductor (BiCMOS) technology, the complementary metal-oxide-semiconductor (CMOS) processing steps are isolated from the bipolar processing steps, in order to avoid implant and process issues between the metal-oxide-semiconductor field effect transistors (MOSFETs) and the bipolar transistors. Additional processing steps are typically required for forming the bipolar transistors, which result in prolonged processing time and increased manufacturing costs.
There is a need for a method for integrating the bipolar transistor processing steps with the conventional CMOS process, with few or no additional processing steps. With system-on-chip (SOC), and network-on-chip (NOC), the demand for digital, analog and RF circuits as well as logic and memory devices on a common chip is high. In wired and wireless communication systems, the desire for CMOS, RF CMOS, RF laterally diffused metal oxide semiconductor (LDMOS), RF BiCMOS SiGe or SiGeC, and gallium arsenide technologies is increasing. As a result, it is desirable to form HBT-based devices with memory, circuits with hysteresis, and high voltage devices, in a common system. Additionally, it is desirable to enable voltage controlling and power controlling applications at 25 V and 40 V by integrate SiGe HBT devices and high voltage circuits.
Further, power control applications over 40 V require electrical static discharge (ESD) networks that have trigger conditions above the power supply voltage. In power technologies that utilize LDMOS transistors require both 25 V and 40 V power supply conditions. In standard CMOS technology, with low voltage junction and well breakdown voltages, the ability to provide ESD networks in this voltage range is impossible. In standard CMOS technology, the breakdown voltages of n-well regions can be below 40 V, which prevent formation of silicon controlled rectifiers (SCRs) in the p-diffusion region, the n-well region, the p-substrate and the n-diffusion region.
There is a continuing need for improved SCRs with higher trigger conditions, which can be employed as ESD structures in greater than 40 V power supply conditions. It is desirable to integrate high voltage elements into CMOS, high voltage CMOS, or RF BiCMOS SiGe systems. Today, there is no such an integrated system with high voltage elements, such as high voltage SCRs, integrated into CMOS or BiCMOS SiGe/SiGeC applications. Additionally, due to the cost associated with BiCMOS technology, it is desirable to form such an integrated system without additional masking steps or cost.